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AU9330 USB Secure Digital Card Reader Technical Reference Manual
Revision 1.0
(c) 2000-2002 Alcor Micro Corp. All Rights Reserved
Copyright Notice Copyright 2000 - 2002 Alcor Micro Corp. All Rights Reserved. Trademark Acknowledgements The company and product names mentioned in this document may be the trademarks or registered trademarks of their manufacturers. Disclaimer Alcor Micro Corp. reserves the right to change this product without prior notice. Alcor Micro Corp. makes no warranty for the use of its products and bears no responsibility for any error that appear in this document. Specifications are subject to change without prior notice.
Contact Information: Web site: http://www.alcormicro.com/ Taiwan Alcor Micro Corp. 4F-1, No 200 Kang Chien Rd., Nei Hu, Taipei, Taiwan, R.O.C. Phone: 886-2-8751-1984 Fax: 886-2-2659-7723 Santa Clara Office 2901 Tasman Drive, Suite 206 Santa Clara, CA 95054 USA Phone: (408) 845-9300 Fax: (408) 845-9086 Los Angeles Office 9400 Seventh St., Bldg. A2 Rancho Cucamonga, CA 91730 USA Phone: (909) 483-9900 Fax: (909) 944-0464
Table of Contents
1.0 Introduction-------------------------------------------------------------------------------------1.1 Description---------------------------------------------------------------------------------1.2 Features-------------------------------------------------------------------------------------1 1 1 3 5 7 7 8 9 9 9 9
2.0 3.0 4.0
Application Block Diagram----------------------------------------------------------------Pin Assignment-------------------------------------------------------------------------------System Architecture and Reference Design----------------------------------------4.1 AU9330 Block Diagram-----------------------------------------------------------------4.2 Sample Schematics------------------------------------------------------------------------
5.0
Electrical Characteristics------------------------------------------------------------------5.1 Recommended Operating Conditions------------------------------------------------5.2 General DC Characteristics -----------------------------------------------------------5.3 DC Electrical Characteristic for 3.3 volts operation -------------------------------
5.4 Crystal Oscillator Circuit Setup for Characteristics ------------------------------ 10 5.5 ESD Test Results -------------------------------------------------------------------------- 11 5.6 Latch-Up Test Results ------------------------------------------------------------------- 12
6.0
Mechanical Information---------------------------------------------------------------------- 15
TABLE OF CONTENTS
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TABLE OF CONTENTS
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1.0 Introduction
1.1 Description
The AU9330 is a single chip integrated USB Secure Digital (SD) card reader controller. It supports Secure Digital (SD) and Multimedia Card (MMC) with automatic card type detection capability. It can be used as a removable storage disk in enormous data exchange applications between PC and PC or PC and various consumer electronic devices. The AU9330 can read Secure Digital card's contents created by handheld consumer electronic devices such as digital camera, MP3 player, PDA and mobile phone.., etc. It provides a faster and convenient way of data transfer scheme to meet the emerging need of a data exchange center between PC and various consumer devices. With AU9330, users' experience will be further enhanced by the Plug-and-Play nature built into latest operation systems such as Windows XP and MacOS X.
1.2 Features
Fully compliant with USB v1.1 specification and USB Device Class Definition for Mass Storage, Bulk-Transport v1.0 Fully compliant with Secure Digital (SD) v1.0 Specification. Work with default driver from Windows ME, Windows 2000, Windows XP, Mac OS 9.1, and Mac OS X. Windows 98 is supported by vendor driver from Alcor. Ping-pong FIFO implementation for concurrent bus operation Support multiple sectors transfer to optimize performance LED for bus activity monitoring Runs at 12MHz, built-in 48 MHz PLL Built-in 3.3V regulator 44-pin LQFP package
INTRODUCTION
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INTRODUCTION
2
2.0 Application Block Diagram
Following is the application diagram of a typical flash memory card reader using AU9330. By connecting the reader to a PC through USB bus, the AU9330 is acting as a bridge between the flash memory card from digital camera, MP3 player, PDA or mobile phone and PC.
Digital Camera
PC with USB Host Controller
MP3 Player
PDA USB Flash Card Reader SD/MMC Card
Moble Phones
PC
APPLICATION BLOCK DIAGRAM
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APPLICATION BLOCK DIAGRAM
4
3.0 Pin Assignment
The AU9330 is packed in 44-LQFP form factor. The following figure shows signal name for each pin and the table in the following page describes each pin in detail.
RESERVED SDDATAO VCC05V SDCMD SDCLK XTAL2 XTAL1 TEST3 GND0 SDCD 44 SDWP 1 RSTN
43
42
41
40
39
38
37
36
35
34 33 RESERVED
GPO6
2
32
GND0
GPO7
3
31
VCC05V
GPI0
4
30
RESERVED
GPI1
5
29
RESERVED
GND0
6
28
RESERVED
GNDI
7
27
RESERVED
VCCI5V
8
26
VCCK5V
VCC3V
9
25
GNDK
USB_DM
10
24
TEST2
USB_DP
11 12 13 14 15 16 17 18 19 20 21 22
23
TEST1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
VCCO5V
TESTE 0
GND0
PIN ASSIGNMENT
5
Table 3-1. Pin Descriptions
pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name SDWP GPO6 GPO7 GPI0 GPI1 GNDO GNDI VCCI5V VCC3V USB_DM USB_DP TEST 0 RESERVED RESERVED RESERVED RESERVED GNDO VCC05V RESERVED RESERVED RESERVED RESERVED TEST1 TEST2 GNDK VCCK5V RESERVED RESERVED RESERVED RESERVED VCC05V GNDO RESERVED RESERVED RSTN GNDO VCC05V TEST3 XTAL1 XTAL2 SDCMD SDCLK SDDATA0 SDCD IO Type I O O I I PWR PWR PWR O I/O I/O NC NC NC NC PWR PWR NC NC NC NC I I PWR PWR NC NC NC NC PWR PWR NC NC I PWR PWR I I O I.O O I/O I Discription SD Write Protect General Purpose Output pin General Purpose Output pin, used as activity LED Should be connected to GND Should be connected to VCC
Regulated 3.3 Volt for DP pull up USB DUSB D+ Should connected to GND
5V input voltage
Should connected to GND Should connected to VCC 5V input voltage
5V input voltage
Hardware reset (Active Low) 5V input voltage Should be connected to GND Crystal Oscillator Input(12MHz) Crystal Oscillator Output(12MHz) SD Card Command SD Card Clock SD Card Data 0 SD Card Detect
PIN ASSIGNMENT
6
4.0 System Architecture and Reference Design
4.1 AU9330 Block Diagram
Alcor Micro - AU9330 Flash Memory Card Reader Block Diagram
USB Upstream Port
XCVR
USB SIE
USB FIFO
DMA Engine
SD/MMC control & FIFO
SD/MMC BUS
Processor
ROM
RAM
3.3 V
3.3 V Voltage Regulator
12MHz XTAL
Reset
SYSTEM ARCHITECTURE AND REFERENCE DESIGN
7
4.2 Sample Schematics
U1 VCC FB B TYPE CONNECTOR J1 VCC DATADATA+ GND FGND1 1 2 3 4 5 C1 0.1UF F1 C2 10UF 1.5K R2 R4 39 39 R1 VCC3.3 FB C3 1UF F2 C4 0.1UF VCC 1 2 GPO7 3 GPI0 4 GPI1 5 GNDO 6 GNDI 7 VCCI5V 8 9 10 11 TESTEN0 12 13 14 15 16 GNDO 17 VCCO5V 18 19 20 21 22 SDWP SDWP GPO6 GPO7 GPI0 GPI1 GNDO GNDI VCCI5V VCC3V USB_DM USB_DP TESTEN0 RESERVED RESERVED RESERVED RESERVED GNDO VCCO5V RESERVED RESERVED RESERVED RESERVED AU9330 VCC3.3 R6 R7 VCC3.3 10K 10K VCC VCCI5V C6 0.1UF C7 GNDI 0.1UF GNDO SDCLK SDDATA0 SDWP VCCO5V C8 0.1UF GNDO VCC FB C9 0.1UF FB F4 F3 VCCK5V C10 0.1UF GNDK C12 C11 18PF R10 Y1 12MHZ XTAL2 SD SOCKET VCC VCCO5V 47K 47K JP1 9 1 2 SDCD 3 4 5 6 7 8 SDWP R8 R9 SDCD SDDATA SDCLK SDCMD XTAL2 XTAL1 PLLTEST VCCO5V GNDO RSTN WAITN RESERVED GNDO VCCO5V RESERVED RESERVED RESERVED RESERVED VCC5K GNDK CPUTEST2 CPUTEST1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 SDCD SDDATA SDCLK SDCMD XTAL2 XTAL1 PLLTEST VCCO5V GNDO R3 GNDO VCCO5V 10K
VCC R3 C5 0.1UF
VCC 470K
VCC5K GNDK
VCC
D1
330
R5
GPO7
ACTIVITY LED
SDCMD SDCD
VCC
XTAL1
18PF 1M
Disclaimer: This schematic is for reference only. Alcor Micro Corp. makes no warranty for the use of its products and bears no responsibility for any error that appear in this document. Specifications are subject to change without notice.
Size A Date:
Document Number AU9330 USB SD/MMC READER DEMO BOARD Friday, December 14, 2001 Sheet 1 of 1
Rev
1.0b
SYSTEM ARCHITECTURE AND REFERENCE DESIGN
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5.0 Electrical Characteristics
5.1 Recommended Operating Conditions
SYMBOL VCC VIN TOPR TSTG PARAMETER Power Supply Input Voltage Operating Temperature Storage Temperature MIN 4.75 0 0 -40 TYP 5 MAX 5.25 VCC 85 125 UNITS V V O C O C
5.2 General DC Characteristics
SYMBOL IIL IIH IOZ CIN COUT CBID PARAMETER Input low current Input high current Tri-state leakage current Input capacitance Output capacitance Bi-directional buffer capacitance CONDITIONS no pull-up or pull-down no pull-up or pull-down MIN -1 -1 -10 TYP MAX 1 1 10 UNITS A A A F F F
5 5 5
5.3 DC Electrical Characteristics for 3.3 volts operation
SYMBOL VIL VIH VOL VOH RI PARAMETER Input Low Voltage Input Hight Voltage Output low voltage Output high voltage Input Pull-up/down resistance CONDITIONS CMOS CMOS IOL=4mA, 16mA IOH=4mA,16mA Vil=0V or Vih=VCC MIN 2.3 0.4 2.4 10k/200k TYP MAX 0.9 UNITS V V V V K
ELECTRICAL CHARACTERISTICS
9
5.4 Crystal Oscillator Circuit Setup for Characterization
The following setup was used to measure the open loop voltage gain for crystal oscillator circuits. The feedback resistor serves to bias the circuit at its quiescent operating point and the AC coupling capacitor, Cs, is much larger than C1 and C2.
ELECTRICAL CHARACTERISTICS
10
5.5 ESD Test Results
Test Description : ESD Testing was performed on a Zapmaster system using the HumanBody -Model (HBM) and Machine-Model (MM), according to MIL_STD 883 and EIAJ IC_121 respectively. Human-Body-Model stress devices by sudden application of a high voltage supplied by a 100 PF capacitor through 1.5 Kohm resistance. Machine-Model stresses devices by sudden application of a high voltage supplied by a 200 PF capacitor through very low (0 ohm) resistance Test circuit & condition Zap Interval : 1 second Number of Zaps : 3 positive and 3 negative at room temperature Critera : I-V Curve Tracing Model HBM MM Model Vdd, Vss, I/C Vdd, Vss, I/C S/S 15 15 TARGET 4000V 200V Results Pass Pass
ELECTRICAL CHARACTERISTICS
11
5.6 Latch-Up Test Results
Test Description: Latch-Up testing was performed at room ambient using an IMCS-4600 system which applies a stepped voltage to one pin per device with all other pins open except Vdd and Vss which were biased to 5 Volts and ground respectively. Testing was started at 5.0 V (Positive) or 0 V(Negative), and the DUT was biased for 0.5 seconds. If neither the PUT current supply nor the device current supply reached the predefined limit (DUT=0 mA , Icc=100 mA), then the voltage was increased by 0.1 Volts and the pin was tested again. This procedure was recommended by the JEDEC JC-40.2 CMOS Logic standardization committee. Notes: 1. DUT: Device Under Test. 2. PUT: Pin Under Test.
Icc Measurement
m 1 Source
V Supply
Vcc Pin under
+
Untested Input Tied to V supply Trigger Source
DUT
GND
Untested Output Open Circuit
+
Test Circuit : Positive Input/ output Overvoltage /Overcurrent
ELECTRICAL CHARACTERISTICS 12
Icc M easurem ent
mA 1 Source Untested Input Tied to V supply Trigger Source
V Supply
Vcc Pin under test
DUT
GND
Untested Output O pen C ircuit
+
+
Test Circuit : Negative Input/ O utput O vervoltage /O vercurrent
Icc Measurement mA V Supply Untested Output Open Circuit
Vcc All Input Tied to V supply
+
DUT
GND Supply Voltage test
Latch-Up Data
Model Voltage Current Vdd-Vxx Model + + Voltage (v)/ Current (mA) 11.0 11.0 200 200 9.0 S/S 5 5 5 Pass 13 Results Pass
ELECTRICAL CHARACTERISTICS
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ELECTRICAL CHARACTERISTICS
14
6.0 Mechanical Information
MECHANICAL INFORMATION
15

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